The present invention relates to technology for manufacturing a semiconductor device, and particularly to technology which can be effectively applied to assembling a semiconductor device which is formed by stacking another substrate on a main surface of a substrate having semiconductor chips mounted thereon.
Recently, there has been increasing demand for larger number of pins on semiconductor devices having semiconductor chips mounted thereon. As a semiconductor device meeting such demand, a BGA (Ball Grid Array) is considered effective, having semiconductor chips mounted on the front surface of a wiring substrate, as well as a plurality of solder balls provided at the rear surface side of the wiring substrate to act as external terminals.
Japanese Patent Laid-Open No. 2007-335581 (Patent Document 1), for example, describes the structure of such a semiconductor device. In addition, a plating layer needs to be formed on the surface of each electrode of the wiring substrate used in the semiconductor device, for which the Patent Document 1, discloses a technique of providing a power supply line for electrolytic plating to form a plating layer on each electrode via the power supply line.
In order to increase the number of pins (for higher functionality) of and to downsize a so-called BGA-type semiconductor device using a wiring substrate, it is desirable to arrange a plurality of electrodes (bonding leads and lands) of the wiring substrate not only on the periphery but also on the central part of the wiring substrate as described in Patent Document 1, for example.
Considering the reliability of the semiconductor device, it is desirable to form a plating layer on the surface of each electrode of the wiring substrate by electrolytic plating as described in Patent Document 1. The reason for this is to enhance the joining strength between each electrode (bonding pad) of the semiconductor chip mounted on the wiring substrate or a conductive member (wire and bump electrode) used when coupling to another electronic component (semiconductor device) mounted on the wiring substrate and an electrode of the wiring substrate.
Although electroless plating may be used to simply form a plating layer, it is desirable to use electrolytic plating since electroless plating requires a longer time to form the plating layer (deposition time of a plating film) than electrolytic plating.
If, on the other hand, by electrolytic plating, it is necessary to draw a wiring (power supply line) from each electrode to the periphery of the wiring substrate to supply electric power to each electrode pad of the wiring substrate, as described in Patent Document 1.
However, it has became difficult in terms of space to individually couple the wiring (power supply line) to each electrode mounted on the central part of the wiring substrate as semiconductor devices are downsized and provided with increased number of pins (for higher functionality).
It is thus effective, as described in Patent Document 1, to reduce the number of wirings (power supply lines) drawn as far as the end portion of the wiring substrate by sharing (using in common) the wirings (power supply lines) coupled to each of the electrodes mounted on the central part of the wiring substrate in a region (inside the electrodes mounted on the central part of the wiring substrate, according to Patent Document 1).
In the semiconductor device examined by the inventors of the present application, however, the number of electrodes formed on the wiring substrate has been further increasing, whereby it has become difficult to share (use in common) all the wirings (power supply lines) coupled to each of the electrodes mounted on the central part of the wiring substrate in the central part (inside the electrodes mounted on the central part side of the wiring substrate). This is because the region in the central part of the wiring substrate (region inside the electrodes mounted on the central part side of the wiring substrate) is narrower (smaller) than the region at the periphery of the wiring substrate (region outside the electrodes mounted on the central part side of the wiring substrate).
The inventors therefore examined sharing (using in common), between the electrodes mounted on the central part side of the wiring substrate and the electrodes mounted on the periphery side of the wiring substrate in the plan view, the wirings (power supply lines) coupled to each of the electrodes mounted on the central part side of the wiring substrate, and encountered the following problems.
Since a common signal (including power source electric potential and reference potential) does not flow in each of the electrodes on the wiring substrate, each of the electrodes on the wiring substrate must be electrically separated from each other after a plating layer has been formed on the surface thereof.
However a crack occurred on the wiring substrate starting from a groove formed on the front surface of the wiring substrate due to the above separation step.
When a crack occurs on the wiring substrate, the crack proceeds along the wiring formed on the wiring substrate, which may lead to a problem of broken wiring and thus it is necessary to take preventive measures against such a crack.
An additional examination of the inventors has revealed that, in the case of Patent Document 1, a shared part of the wiring (power supply line) to be removed by the separation step is provided beneath the semiconductor chip (a part covered by the semiconductor chip) and a groove formed by the separation step is filled with a die-bonding material (adhesive agent) for mounting the semiconductor chip, and thus the crack is less likely to start from the groove.
The present invention has been made in view of the above circumstances and provides technology which can improve the reliability of a semiconductor device.
It is another object of the invention to provide technology which can increase the number of pins on a semiconductor device.
It is also another object of the invention to provide technology which can downsize a semiconductor device.
The above and other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.